Circuit arrangement for balancing of a push-pull output stage of the invention, the output stage transistors complementary protudes

• 1. 一种适用于推挽输出级LDO的电流限制电路 [P] . 中国专利： CN106936304B . 2018.11.23
• 2. 一种适用于推挽输出级LDO的电流限制电路 [P] . 中国专利： CN106936304A . 2017-07-07
• 3. Low frequency amplifier exhibiting a push-pull output stage, with complementary - transistors in the collector circuit [P] . 德国专利： DE1298571B . 1969-07-03

  机译： 低频放大器具有推挽输出级，集电极电路中具有互补晶体管

• 4. Circuit arrangement for push-pull output stages - b - with power transistors and galvanically coupled with these transistors. [P] . 德国专利： DE1190990B . 1965-04-15

  机译： 推挽输出级的电路布置-b-具有功率晶体管，并且与这些晶体管电耦合。

• 5. Circuit arrangement for transistor oris is either nf - push-pull output stages in bzw.quasikomplementaerschaltung [P] . 德国专利： DE1801198A1 . 1970-05-14

  机译： 晶体管Oris的电路布置为bzw中的nf-推挽输出级.quasikomplementaerschaltung

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• 1. Controlling the output power of soft switching arc welding inverter by two-stage continuous PWM method [J] . Fu Qiang ,Zhao Shanqi ,Fan Xinnan . 中国焊接 . 2016,第001期
• 2. Life Cycle Input-Output Analysis Extended to Use, Disposal, and Recycling Stages Applied to Embodied CO2 Emissions of a Refrigerator [J] . Yuki Mizumoto ,Yohji Uchiyama ,Keiichi Okajima . 能源与动力工程 . 2013,第004期
• 3. Performance Analysis on Output SINR of Robust Two-Stage Beamforming [J] . Tsui-Tsai Lin ,Fuh-Hsin Hwang ,Juinn-Horng Deng . 信号与信息处理（英文） . 2011,第1期
• 4. 一种改进输出级的四相位时钟电荷泵电路 [C] . 张梦欣 ,李建成 . 第二十届计算机工程与工艺年会暨第六届微处理器技术论坛 . 2016
• 5. 通信接口电路输出级模拟方法研究 [A] . 朱文戈 . 2013