Simplified partial double error correction using single error correcting code

摘要

1,057,985. Error correction. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 8, 1964 [May 13, 1963], No. 19347/64. Heading G4C. A digital data word comprising information and parity bits in accordance with a Hamming single error correcting code is assembled in parallel form from bits occurring on a number of separate lines each of which supplies a serial pair of bits, double errors being corrected on the assumption that both bits in error occurred on the same line. In the particular embodiment, a 16-bit word comprising 11 information bits and 5 parity bits is read from a set of eight magnetic disc stores and assembled in parallel form. EXCLUSIVE-OR circuitry performs parity checks to produce error signals E0, E1, E2, E4, E8 (all " zero " in the absence of errors). If E0, which relates to the whole word, is " one," there is assumed to be a single error (rather than 3, 5 or &c.) and the error signals E1, E2, E4 are allowed by gating circuitry (Fig. 8, not shown) to constitute the input to one of two binary to decimal decoders (no details given) depending on the value of signal E8. The selected decoder produces an output on one of eight lines leading to EXCLUSIVE- OR gates to correct the bit in error. If both signals E0 and E8 are " zero", there is an uncorrectable double (or strictly, even) error and an alarm signal is generated. If signals E0 and E8 are " zero " and " one " respectively, both binary to decimal decoders receive signals derived from the error signals E1, E2, E4 (see Figs. 8, 10, not shown) by EXCLUSIVE-OR gates and two errors are corrected. Thus when a double error occurs and it is consistent with the results of the parity checks to assume that both bits in error came from the same disc, corrections are made on these assumptions, whereas when only the first assumption is consistent, the errors are declared uncorrectable.