Error detector arrangement for determining when reading a computer memory faults occurring

摘要

1284117 Error detection or pulse circuits HONEYWELL Inc 9 Sept 1969 [28 Oct 1968] 44457/69 Heading H3P [Also in Division G4] An error detecting apparatus comprises means 201 for producing digital signals, storage means 204, 206 for receiving the signals and having a reset state and at least second and third further states, and checking means comprising a first means 212 for producing an error signal if the storage means are not in the reset state after a reset signal but before receiving said signals, and second means 238 for producing an error signal if the storage means are in the reset state after receiving said signals. The read pulses pass to a digital computer via lines 248, 250. A read only memory is formed of ferrite cores using two cores 224, 226 per bit, the one core always being in an opposite state to the other. A drive line 202 threads the two cores and sense lines 200 feed a differential amplifier 228 to give the output 221, 223 indicated (or vice versa, depending on the core state) when line 202 is pulsed. The output is connected to flip-flop 204, which is only set by a pulse 221, and a flip-flop 206, which is only set by a pulse 223. Operation.-The flip-flops 204, 206 are reset to binary 1 by means 208, and a first error test checks whether this has been effected by means of an AND gate 212 which is only enabled if both flip-flops are reset and a first signal generator 214 pulses at that time. Then the drive line 202 is pulsed by timing unit 210 and signals 221, 223 are generated. One flip-flop is set by signal 221 and immediately after the other flip-flop is inhibited by line 232 or 234. The second error test checks whether signal 221 has been read using AND gate 238 which is pulsed at that time by generator 236. If 221 has been read, line 242 will read 0 and line 244 will read 1 and no error signal 246 will be sent. If, however the signal 221 has not been read, an error signal 246 will be sent since line 242 will read 1. If this happens pulse 223 will set one flip-flop but, by this time, the error signal will have been sent. A number of such bits are read in parallel using one source of clock pulses. Any number of storage states greater that two may be used for a number of lines or one line having a number of signals.