method for analog digital implementation with improved differentiallinearitaet implementation

摘要

A known process and apparatus for analog-to-digital conversion includes a storage circuit SP which includes a capacitor C which receives a charge corresponding to the voltage of an analog signal I to be measured, thereafter counts the change in charge of this circuit in two steps. During the first step of the process the stored circuit (SP) is discharged at a discharge rate adjusted to the coding rate. The discharge rate employed in the second step of the process is lower than the rate used in the first step. Accordingly, during the first step current from a source S1 is applied to the storage circuit SP at a higher rate than in the second step and a correspondingly higher evaluation of pulses from a timing generator TG which are counted in a counter Z occurs, and during a second step the storage circuit SP receives current from a current source S2 at a lower rate and a corresponding lower evaluation of pulses occurs. The expression "higher evaluation" means that the time-measuring impulses of the timing generator counted in the counter during the discharge of the first step of the process must have a greater weight than the impulses counted in the second step. To this end, counting impulses are added directly to counting stages of higher significance. This known apparatus is improved in the present invention by utilizing the current source S2 as an additional voltage to be added to the analog voltage in storage, prior to the first step of the process, and in an amount controlled by the number of analog values to be converted in succession. At the same time as this additional voltage is added, a correspondingly evaluated number of counting pulses are delivered to the counter Z.