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Device for forming the exponent in the case of converting a binary number of the fixed point in the sliding point representation

机译:在滑动点表示中转换固定点的二进制数的情况下用于形成指数的装置

摘要

1,076,207. Digital electric calculating apparatus. SPERRY RAND CORPORATION. Dec. 7, 1964 [Dec. 31, 1963], No. 49645/64. Heading G4A. In an arrangement for normalizing and generating the scale factor of a binary number, the number is shifted one place to the right and compared with the original number, the highest order bit position in which there is a difference providing an indication of the scale factor and hence the number of shifts required to normalize the number. The apparatus described can effect either one of two normalization operations on 36-bit (including sign bit) binary numbers: (1) " normalize floating point " in which the result is an 8-bit scale factor and a 27-bit mantissa, plus sign bit; (2) "normalize non- floating point " in which the result is a 7-bit scale factor and a 35-bit mantissa, plus sign bit. The arrangement has the advantage over known arrangements in which the number to be normalized is shifted, that the time of the normalization operation is independent of the position of the most significant digit in the number. In operation, for a " non-floating point " normalization, the number to be normalized is placed in an A register, Fig. 1 and gated directly to an X register and, with a shift of one place to the right, to a D register. The contents of the A and D registers are then compared, the comparison being effected by employing halfadders in the stages of a parallel adder 1 to compare the individual bits in the various stages of the two registers. The 35 significant bit outputs of the comparison operation are arranged in four 8-bit groups A-D and one 3-bit group E, an arrangement of group selectors A-D, Fig. 3 (not shown) and associated gates 90-93 being arranged to provide an output on one of five leads indicating which of the five groups contains the highest order comparison difference. The four leads from selectors A-E are connected to a group translator 100 (shown in detail in Fig. 5, not shown) which produces outputs on leads 94-96 representing the three highest order digits of the 7-bit scale factor number. The outputs of the group selector circuits also render operative one of five gating circuits in the input to a bit translator 101, thereby causing the comparison digits in the selected group to be translated by the translator 101 (which is shown in more detail in Fig. 5) to provide outputs on leads 97-99 indicating the three lowest order digits of the scale factor number. The scale factor number, which is called a " left shift count " since it indicates the number of single shifts to the left required, is subtracted from the value 72 in a subtracter 103 to provide a " right shift count ", since the shift matrix, top right of Fig. 1, can effect directly only a shift to the right by up to 72 places. The left shift is entered in a register K1, Fig. 1, and the right shift count in a register K3 where its seven bits control the shift matrix, which comprises three gating levels responsive respectively to stages 0, 1; 2, 3; 4, 5, 6 of the register K3. The number to be normalized is now transferred over a bus 41 to the shift matrix where it is shifted by gating by the appropriate number of places to enter the significant digits in the high order places of the D register. The scale factor K2 is then transferred, to the X register. A floating point normalization is generally similar, but a right shift instead of a left shift may be necessary if the highest significant digit is in any of bit positions 27-34. If a left shift is necessary, a positive sign in the number being normalized is effective to complement the scale factor register K2 by subtraction from zero at 5, Fig. 1. The sign bit and scale factor are transmitted to bit positions 35, 27-34, respectively, in the D register to produce the normalized floating point number. If a right shift is necessary in a floating point normalization, the right shift count is supplied to register K3 as before, and its complement is transferred to the scale factor register K1, the sign of the original number in the A register determining whether a further complementation is necessary to produce the correct scale factor.
机译:1,076,207。数字电子计算设备。斯普瑞兰德公司。 1964年12月7日[12月[1963年1月31日],第49645/64号。标题G4A。在用于归一化并生成二进制数的比例因子的布置中,该数字向右移动一位,并与原始数字进行比较,其中存在差异的最高阶位位置提供了比例因子的指示,并且因此,将数字标准化所需的移位次数。所描述的设备可以对36位(包括符号位)二进制数执行两个规范化操作之一:(1)“规范化浮点”,其结果是8位比例因子和27位尾数,加上符号位(2)“归一化非浮点”,其结果是7位比例因子和35位尾数加符号位。该安排优于已知安排,在该安排中,要归一化的数字被移位,归一化操作的时间与该数字中最高有效数字的位置无关。在操作中,对于“非浮点”归一化,要归一化的数字放置在图1的A寄存器中,并直接选通到X寄存器,并向右移一位,移至D寄存器。然后比较A和D寄存器的内容,该比较是通过在并行加法器1的各级中采用半加法器来比较两个寄存器各个级中的各个位来实现的。比较操作的35个有效位输出布置在四个8位组AD和一个3位组E中,图3(未示出)的组选择器AD的布置以及相关联的门90-93布置成提供五个引线之一上的输出,指示五个组中哪个包含最高阶比较差。来自选择器A-E的四个引线连接到组转换器100(在图5中详细示出,未示出),其在引线94-96上产生表示7位比例因子数的三个最高阶数字的输出。组选择器电路的输出还在比特转换器101的输入中使五个选通电路之一起作用,从而使所选组中的比较数字由转换器101翻译(在图2中更详细地示出)。 5)在导线97-99上提供输出,指示比例因子编号的三个最低位数字。由于减法器矩阵中的比例因子数表示所需的向左单移的次数,因此它被称为“左移计数”,在减法器103中从值72中减去它,以提供“右移计数”。图1右上方的,最多只能直接向右移动72个位置。左移位输入到图1的寄存器K1中,右移位计数输入到寄存器K3中,其中的7位控制移位矩阵,移位矩阵包括分别响应级0、1的三个门控电平;和2 3寄存器K3的4、5、6。现在,将要归一化的数字通过总线41传输到移位矩阵,在该矩阵中通过门控移位适当的位数,以将其有效数字输入D寄存器的高位。然后将比例因子K2传输到X寄存器。浮点归一化通常类似,但是如果最高有效位在任何位置27-34中,则都需要右移而不是左移。如果需要左移,则通过在图1的5处减去零,正数中的正号可以有效地对比例因子寄存器K2进行补充。符号位和比例因子被传输到位位置35、27- 34,分别在D寄存器中生成归一化的浮点数。如果在浮点归一化中需要右移,则将右移计数像以前一样提供给寄存器K3,并将其补码传输到比例因子寄存器K1,A寄存器中原始数字的符号确定是否还要为了产生正确的比例因子,必须进行互补。

著录项

  • 公开/公告号DE1474080B2

    专利类型

  • 公开/公告日1971-11-18

    原文格式PDF

  • 申请/专利权人

    申请/专利号DE19641474080

  • 发明设计人

    申请日1964-12-28

  • 分类号G06F7/38;

  • 国家 DE

  • 入库时间 2022-08-23 08:38:26

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