ADAPTIVE LOGIC SYSTEM FOR UNSUPERVISED LEARNING

摘要

1,264,888. Adaptive logic. INTERNATIONAL BUSINESS MACHINES CORP. 13 Nov., 1969 [29 Nov., 1968], No. 55556/69. Heading G4R. Adaptive logic units are adapted only if a predetermined output signal is followed by a further output signal occurring in the second of two consecutive timing periods following the production of the predetermined output signal. A binary input pattern is applied to each of a plurality of threshold logic circuits each of which obtains a weighted sum of the bits using potentiometers and a summing amplifier and then compares the sum voltage with a falling ramp voltage applied to all the logic circuits simultaneously to produce an output pulse when the ramp falls below the sum voltage. The first output pulse sets a first latch respective to the logic circuit, sets a control latch to disable gates to prevent later output pulses affecting the first latches, and initiates two single-shots of different durations. If the next output pulse occurs while the shorter-duration single-shot is on, a reset pulse is applied to the first latches. On the other hand, if this output pulse occurs while the longer-duration single-shot is on but the shorter is off, a second latch respective to the logic circuit is set and applies a decrement signal to this logic circuit and causes the set first latch to apply an increment signal to its logic circuit. The increment and decrement signals adjust in respective senses those potentiometers which correspond to input bits which are 1. System output is from the first latches. A second embodiment differs in taking system output from third latches each of which is set by an output pulse from a respective one of the logic circuits. The first output pulse initiates a third single-shot in addition to those above (this may have the shortest duration of all) and if the second (or any later) output pulse occurs while it is on, a reset pulse is applied to the third latches.