APPARATUS FOR PROVIDING A CONTROL SIGNAL INDICATIVE OF ANY DEVIATION OF THE SPEED OF MOVEMENT OF A MOVING OBJECT FROM A DESIRED SPEED

摘要

1317260 Fluidic servosystems PLESSEY TELECOMMUNICATIONS RESEARCH Ltd 25 June 1971 [2 June 1970] 26575/70 Heading G3P A speed control system, e.g. for an engine, includes a rotary code disc with a plurality of code tracks, logic means to sample the code tracks at equal time intervals and provide an output signal if the difference between successive samples is more than a predetermined amount, and integration means to receive and integrate any of said output signals and thereby generate a speed control signal. Although the system may be electronic, it is particularly suited to fluidic control and in one such embodiment comprises a code disc 14 having a three-bit Gray code which is sampled at 2 millisecond intervals established by oscillator 22. Successive samples are stored at 18, 20 and subtract circuit 23 is arranged to produce an output of +1 or -1 each time successive samples differ by more than a predetermined amount in one direction or the other. Counter 24 establishes in store 26 the algebraic sum of all the outputs occurring in a 32 millisecond time interval determined by oscillator 27. The output from the store 26 is fed to D/A convertor 28 which controls engine speed. Variation of the governed speed may be effected by injecting additional pulses into counter 24 during each sampling period, by resetting the counter to other than zero, or by introducing an analog bias at 28. Where an integral output is required, an additional counter may receive the output from store 26 and be reset only at long intervals. The output from converter 28 may also be integrated and differentiated. In a second embodiment, counter 24 and store 26 are replaced by a leaky integrator which, as before, integrates sixteen 2-millisecond samples from a code disc. In a third embodiment, Fig.3, the Gray-to-binary converter is omitted, and the circuits operate directly on the Gray code. As shown, bistable sampling circuits 56, 58, 60 supplied with timing pulses at 2 millisecond intervals from 62 feed coincidence detectors 64, 66, 68 each comprising AND gates 70, 74, 2-millisecond delays 72, 76 and a NOR gate 78 so that the latter provides an output to NOR gate 80 except when consecutive ones or noughts are received from the respective sampling circuit. Leaky integrator 82 has a time constant providing for integration of sixteen 2-millisecond samples.