Fail-safe three-channel clock generator - controls three shift registers using pulse generated by three square-wave generators

摘要

The input variables of the three shift registers are logic functions of the output variables according to the linkage of a 2 to 3 majority logic. The errors of the three output variables across the shift registers are stored in associated storage elements by means of a fail-safe error monitoring circuit according to logic functions of the 2 to 3 majority logic, taking into consideration the transmit time differentials by the delay elements. The warning lights indicate the errors. The error monitoring circuit consists of fail-safe components. The output signals of the rror monitoring circuit become zero in the event of an internal error.