The clock generator is pref. for data flow control in systems where failure could lead to serious consequences, e.g. nuclear power plant or railway signalling. The pulses from three separate square wave generators control three shift registers whose inputs are logic functions of their output based on a 2 from 3 majority logic. The latter is pref. provided by a circuit comprising fail-safe AND and OR elements. The clock pulses are synchronous for all three channels, despite the fact that the square wave generators are non-synchronous.
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