ADMITTANCE-MATCHING NETWORK FOR THE PARALLEL CONNECTION OF WIDE-BAND ACTIVE POWER ELEMENTS

摘要

1384942 Admittance matching network THOMSON-CSF 13 April 1972 [13 April 1971] 17179/72 Heading H3U An admittance matching network connecting an input port to n(n1) output ports comprises p(p1) stages of four terminal network units, F 1 , F 2 , each stage comprising groups of q(q1) such networks, the q networks of each group having their inputs connected in parallel to one of the networks of the preceding stage, so that n = qSPp/SP. In Fig. 2, p = q = 2. Balancing resistors U between outputs may be provided, to compensate for unequal characteristics amongst the n loads. A network unit may comprise an L-C circuit, Fig. 3 (not shown), or a capacitor or transistor together with a wire contributing inductance. Integrated circuit embodiment, Figs. 5, 6 (not shown).-An earthed heat sink (48) supports an input capacitor (C1) of ceramic, thin film or metal oxide semi-conductor construction connected to capacitors (C 2 , C 3 ) of similar construction and thence to the bases of transistors (T 1 -T 4 ), whose emitters are earthed to heat sink (48), via leads (51-54), network units comprising: C 2 , M; C 3 , N; input capacitances of (T 1 -T 4 ) and (43-46) respectively. Balancing resistor (42) is formed by vaporization, or doping impurities on a semi-conductor. The transistors are formed on beryllium oxide substrate (47). Stray inductance of leads (M, N, 43-46) thus play an essential part in determining the network unit characteristics. The loads may comprise transistor amplifiers, avalanche oscillators, or gunn diodes.