An interfacing circuit for restoring voltage pulses to a desired fixed level. The circuit is particularly adapted to CMOS technology and includes features which result in rapid output rise and fall times, latching of the output voltage level, and isolation of the input following transition of the input voltage between its respective final levels. The circuit is also relatively insensitive to noise since it requires voltage transitions greater than the FET threshold levels to fully activate and switch the latching circuit means.
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