首页> 外国专利> Method of fabricating field effect transistors having self- registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors

Method of fabricating field effect transistors having self- registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors

机译:具有在栅电极和金属互连线之间具有自对准电连接的场效应晶体管的制造方法以及包含该晶体管的集成电路的制造

摘要

A method of fabricating a field effect transistor (FET) wherein a self- registered or misregistration tolerant electrical connection is provided between the gate electrode and a metallic interconnection line. The method involves a unique structure which includes a thick deposited oxide insulation layer and an etch stopping layer over doped silicon source and drain regions, over polysilicon gate electrode regions, and over field isolation regions. The etch stopping layer facilitates fabrication of a self-registering electrical connection between the gate electrode and a metallic interconnection line wherever desired. The thick deposited oxide layer provides reduced capacitive coupling between the insulated regions and the metallic interconnection line when compared to known self- registered gate contacting methods that employ only thermally grown oxide insulation. The method also includes the provision for controlling the removal of insulation over the gate electrode wherever desired without seriously degrading the insulation over other parts of the structure. The disclosed method further relates to fabricating an integrated circuit containing FETs having a self- registered electrical connection between the gate electrode and the metallic interconnection line, the gate electrode self-aligned with respect to the source and drain regions, and wherein FETs of the integrated circuit have: a channel region; a gate insulator; an electrically conductive gate electrode; source and drain regions; thick insulation over the source and drain and over the gate electrode except in the contact areas; field isolation or field shield regions between FETs of the integrated circuit; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line.
机译:一种制造场效应晶体管(FET)的方法,其中在栅电极和金属互连线之间提供自对准或不对准误差的电连接。该方法涉及独特的结构,该结构包括在掺杂的硅源极和漏极区上方,多晶硅栅电极区上方以及场隔离区上方的厚沉积的氧化物绝缘层和蚀刻停止层。蚀刻停止层有利于在需要时在栅电极和金属互连线之间制造自对准电连接。与仅采用热生长氧化物绝缘层的已知自对准栅极接触方法相比,厚的沉积氧化物层在绝缘区域与金属互连线之间提供了减小的电容耦合。该方法还包括在需要时控制栅电极上的绝缘层的去除而不会严重降低结构的其他部分上的绝缘层的措施。所公开的方法还涉及制造包含FET的集成电路,该FET在栅电极和金属互连线之间具有自对准的电连接,该栅电极相对于源极和漏极区域自对准,并且其中集成的FET电路具有:一个通道区域;栅极绝缘体;导电栅电极;源极和漏极区域;源极,漏极和栅电极上的绝缘层较厚,接触区域除外;集成电路的FET之间的场隔离或场屏蔽区域;金属型高电导率互连线;栅极和互连线之间的自对准电连接。

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