Stages sensitive, as a monolithic highly integrated circuit convicted out system of logic circuits having embedded therein a matrix arrangement

摘要

P logic system, in general for all the units and modular arithmetic and logical and their control memory associated with any other network and / p & & p & the system is divided into sections formed of a combinational logic arrays 41, 42, of circuits of the storage and of the network 43. Two independent clock c1, c2, are used to control the flip-flops. A control of the delay of one side only, is carried out in the system. The control of the timing of the sets of flip-flops 44, 45 is made so that the system operates independently of the internal time. With each flip-flop is associated with an additional circuit so that each lever operates as a position of a shift register having inputs / outputs and the controls of the offset independent of the clocks of the system. The flip-flops are coupled in the shift register. / p