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Bias circuitry for stacked transistor power amplifier stages
Bias circuitry for stacked transistor power amplifier stages
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机译:堆叠晶体管功率放大器级的偏置电路
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摘要
Stacked transistor power amplifier stages in an integrated-circuit quasi-linear amplifier are supplied quiescent bias currents which are in inverse proportion to their forward current gains. This permits selection of their quiescent collector currents to be at sufficiently low levels to reduce to low values both cross-over distortion and quiescent dissipation.
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