Two phase logic clock source - is based on cross coupled NAND=gates driven from common source

摘要

The clock source is for logic circuits where high precision timing is required, the design requiring a min. number of components without reduction of performance. The circuit is driven from a single source clock whose output is split into two parallel channels feeding two cross coupled NAND or NOR gates (2, 3) one of which has an inverter (1) in its input line. Each gate has a third input point to permit sampling signals to be fed in, the gate outputs feeding two directly coupled inverting amplifiers (m1, m2) which provide buffering and matching into the load circuits. The entire circuit may be monolithic and built onto a common substrate or built up from discrete components.