Rate converter for digital signals having a negative feedback phase lock loop

摘要

An arrangement responsive to input digital signals for producing output digital signals at a higher rate together with stuffing pulses comprises a first frequency divider responsive to input clock pulses defining the rate of the input signals for producing write-in pulses for storing the input digital signals in a memory. A voltage controlled oscillator produces output clock pulses at the higher rate, which pulses are supplied directly and through a circuit responsive to the output clock pulses for supplying stuffing-pulse-position specifying pulses to a second frequency divider for producing read-out pulses for making the memory produce the output signals. A controller responsive to the input clock, output clock, and position specifying pulses and coupled to the first and second frequency dividers establishes a difference in phase between the write-in and read-out pulses which lies in a range wherein a phase lock loop means responsive to the phase difference for controlling the oscillator always carries out negative feedback to the oscillator.