Data processor with interference suppression system - has clock pulses generated in random or pseudo-random fashion to reduce harmonics

摘要

The data processor is designed to reduce the risk of interference to frequency-selective circuits and devices, such as radio receivers, caused by harmonics of the synchronising clock-pulse frequency, without the use of expensive filters. It has applications in computers used in aircraft. The clock-pulse generator built into or separate from the data processor is frequency or phase modulated by means of a noise generator to provide random or stochastic timing of the pulses. This can be achieved by using the output of a shift-register which has feedback. Random variation of the pulse-width of successive pulses may be employed as an alternative.