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Microprocessor memory direct accessing system - has buffer interface controlling data addressing and transfer between memory, drive circuit and logic circuitry

机译:微处理器存储器直接访问系统-具有缓冲器接口,用于控制数据寻址以及存储器,驱动电路和逻辑电路之间的数据传输

摘要

The system comprises a buffer interface (5) which during a period of accessing of the drive circuit from a memory supplies data addresses contained in the memory. It also maintains the continuous circulation of corresponding data between the drive circuit and the memory. This also operates during the rest of the drive circuit accessing period and puts into memory the required data till the termination of the accessing period. It can also operate to break the data circulation towards the memory and the corresp. logic circuitry to control the buffer interface inhibition.
机译:该系统包括缓冲器接口(5),该缓冲器接口在从存储器访问驱动电路的期间提供存储器中包含的数据地址。它还保持驱动电路和存储器之间相应数据的连续循环。在其余的驱动电路访问期间,它也将运行,并将所需的数据存储到存储器中,直到访问期间结束为止。它还可以中断数据流向内存和相应地址。逻辑电路控制缓冲区接口禁止。

著录项

  • 公开/公告号FR2406250A1

    专利类型

  • 公开/公告日1979-05-11

    原文格式PDF

  • 申请/专利权人 TEXAS INSTRUMENTS FRANCE;

    申请/专利号FR19770031140

  • 发明设计人 GERARD CHAUVEL;

    申请日1977-10-17

  • 分类号G06F13/00;

  • 国家 FR

  • 入库时间 2022-08-22 19:32:45

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