首页> 外国专利> Making semiconductor crystals dopant boundaries visible - by etching using high frequency glow discharge and examining with scanning electron microscope

Making semiconductor crystals dopant boundaries visible - by etching using high frequency glow discharge and examining with scanning electron microscope

机译:通过使用高频辉光放电进行蚀刻并使用扫描电子显微镜进行检查,使半导体晶体的掺杂物边界可见

摘要

The boundaries are present in semiconductor crystals, and are esp. pn-junctions in silicon integrated circuits. A sample of the circuit is broken at the zone which is to be examined and then etched via a high frequency (h.f.) glow discharge so the resulting contrast in topography is visible in a scanning electron microscope. The fracture of the sample is pref. made at 90 degrees to the surface of the crystal. When the semiconductor crystal is Si, etching is pref. in a plasma formed from CF4 gas with a sample temp. of =150 degrees C; and the etching time is pref. 2 mins. for revealing n+ zones on p-doped silicon. Plasma etching pref. occurs at a partial pressure of ca. 0.7 torr. with a h.f. source of 200 watts power. Used as an inspection technique in obtaining the min. surface area for individual elements such as diodes, transistors, resistors etc. in integrated circuits, i.e. to achieve the highest packing density.
机译:边界存在于半导体晶体中,尤其是。硅集成电路中的pn结。电路样品在要检查的区域破裂,然后通过高频(h.f.)辉光放电进行蚀刻,因此在扫描电子显微镜中可以看到形貌上的对比度。样品的断裂是优选的。与晶体表面成90度角。当半导体晶体是Si时,蚀刻是优选的。在CF4气体和样品温度下形成的等离子体中。 > = 150摄氏度;并且蚀刻时间是优选的。 2分钟用于揭示p掺杂硅上的n +区。等离子蚀刻发生在约分压。 0.7托与h.f. 200瓦电源。在获得最小值时用作检查技术。集成电路中单个元件(例如二极管,晶体管,电阻器等)的表面积,即达到最高封装密度。

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