Address decoder for dynamic semiconductor memory - has addressing vertical FETs, each with auxiliary transistor whose drain terminals are coupled to FET source terminals

摘要

The address decorder is produced as a MOS integrated circuit. The number of address field-effect transistors corresponds to the number of address bits. Each transistor gate is controllable via an address line. These transistors are connected with a feed transistor to form a NOR-gate, whose signal output serves to activate the addressed memory. Each address transistor (TA) is formed by a vertical structure FET with an auxiliary address transistor (TAH). Each auxiliary transistor drain terminal is connected to each source terminal of the address transistors and the source terminal of the feed transistor at the nodal point (1), forming the NOR-gate signal output. The auxiliary diffused regions ensure that the respective transistor is blocked at the zero gate voltage, while being conductive at the operational gate potential.