Shift register control for video signal generation - samples photodetectors for storage in register using clock control to avoid interference signal effects

摘要

A shift register used in a video signal generation system operates to a clock cycle that eliminates the possibility of distortion effects. The shift register has e.g. 256 memory cells, with data being moved from the left to the right. The output stage (8) transmits signals serially to an output stage (12) for amplification before transmission. A reset facility (14) allows the stage to be cleared after a specified interval. In parallel with the shift register cells are a similar number of photo detector cells (P256-P1) that are sampled within a given period and the charges entered into the register. The signal transfers take place under control of clock signals (4, 5, 6) to form a video signal. The clock signals are phased to prevent the occurrence of disturbances between successive video signals.