Digital semiconductor storage cell synchronisation - checks digital operating states of storage chains and controls cells by clock pulse signal from common pulse generator

摘要

A master storage cell chain (TM) is to change state with each clock pulse and in synchronism with a slave storage cell chain (TS) using the same clock pulses. Interference can cause loss of cynchronisation. The master chain amplitude modulates the clock pulses at intervals determined by the state of the master chain. A signal recognition circuit (SES) recognises the amplitude modulated pulses and triggers a correcting circuit (KSE) to set or reset the slave chain so as to be re-synchronised with the master.