Output stage for bucket brigade circuit - has gate side terminal of last transistor delaying capacitor coupled to source of output transistor

摘要

The bucket brigade circuit is formed by IGFETs of enrichment type with controlled current paths in series. Their drain and gate terminals are each bridged by a capacitor. The gate terminals are controlled by a clock pulse signal, the gate terminals of even transistors being controlled by a signal of identical frequency. The output circuit has a terminal transistor in series with the last delaying transistor of the bucket brigade circuit. The gate terminal of the capacitor (Cn), associated with the last delaying transistor (Tn) in not connected to this gate terminal, but to the source terminal of the output transistor (Tb). The gate terminal of the terminal transistor (Ta) is connected, across an additional capacitor (Cz), to the clock pulse signal (F1) to which is connected the penultimate delaying transistor (Tm).