Logic module or logic means for or in an integrated digital circuit

摘要

There is described a logic module, for an integrated digital circuit, for promoting testing of the latter, and which module comprises latch means having a plurality of basic cells comprising flip-flops FF, each flip-flop FF having an input associated with respective logic gates including an exclusive-OR gate. The said latch means has an input SIN, a multiplexer, parallel data inputs D0 to D3, signal control lines for control signals B0, B1, and a feed-back line leading via a further exclusive-OR gate to the multiplexer. When B0 = B1 = 1, as in the mode shown, the latch means functions as a latch (buffer); when B0 = B1 = 0, the latch means functions as a linear shift register; and when B0 = 1 and B1 = 0, the latch means functions as a back-coupled shift register with parallel data input at D2 and D3 and useable in testing operations. The arrangement enables internally-arising test data to be monitored in parallel. In a modification, there is omitted the line for control signal B0 and the multiplexer is also omitted, this modified embodiment being able to function as a latch (buffer) and as a back-coupled shift register with parallel data-input, but not as a linear shift register. IMAGE