首页> 外国专利> Integrated injection logic circuit with reduced injection current - achieved by locally modifying near surface doping of lateral transistor base

Integrated injection logic circuit with reduced injection current - achieved by locally modifying near surface doping of lateral transistor base

机译:降低注入电流的集成注入逻辑电路-通过局部修改横向晶体管基极的近表面掺杂实现

摘要

In the case of an PNP type lateral transistor the near surface region (6) of the base is of type N plus and is formed at the same stage as the collectors (5) of the vertical NPN transistor. This modified region neither touches nor intersects the emitter or collect regions. This technique permits structures to be used which would not formerly work because of excessive injection current and linear components to be integrated on the same dice without degrading switching speed and chip density of significantly increasing cost.
机译:在PNP型横向晶体管的情况下,基极的近表面区域(6)是N plus型,并且形成在与垂直NPN晶体管的集电极(5)相同的阶段。该修改区域既不接触也不与发射器或收集区域相交。这种技术允许使用以前由于过大的注入电流而无法工作的结构,并且将线性元件集成在同一芯片上,而不会降低开关速度和芯片密度,从而大大增加了成本。

著录项

  • 公开/公告号FR2460038A1

    专利类型

  • 公开/公告日1981-01-16

    原文格式PDF

  • 申请/专利权人 THOMSON CSF;

    申请/专利号FR19790016557

  • 发明设计人 MAURICE DEPEY;

    申请日1979-06-27

  • 分类号H01L21/72;H01L27/04;

  • 国家 FR

  • 入库时间 2022-08-22 15:04:24

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