Successive approximation S/D converter with inherent quantization error centering

摘要

A comparator network in a successive approximation synchro-to- digital converter uses two comparators to determine the quadrant of the synchro angle and then uses one of these comparators as a steering voltage comparator to determine the less significant bits of the synchro angle. Fractions of the sine and cosine analog inputs are cross-coupled to the comparators to provide inherent quantization error centering.