ARRANGEMENT OF ANTHEMOIRES COMPRISING A BUFFER ANEMEMORY IN COMBINATION WITH A PAIR OF ANTEMEMORY

摘要

IN THE ARRANGEMENT BETWEEN A CONTROL PROCESSOR 21 AND A MAIN MEMORY 22, INCLUDING OPERAND AND INSTRUCTION ANTEMEMORIES 31, 32, A BUFFER ANTEMEMORY CIRCUIT RESPONDS TO STORAGE REQUESTS FROM THE PROCESSOR TO STORE STORAGE DATA AND STORAGE ADDRESS AND PRODUCE SUCH STORED DATA AS OUTPUT DATA AND OUTPUT ADDRESS FROM THE BUFFER MEMORY SIMULTANEOUSLY TO A REQUEST FOR STORAGE IN BUFFER MEMORY. RESPONDING TO THIS REQUEST, THE CONTROL CIRCUITS 36, 37 OF THE FIRST AND SECOND ANTEMEMORIES TRANSFER THE MEMORY OUTPUT ADDRESS DATA TO THE MEMORIES 31 AND 32 IF EACH OF THEM IS NOT SUPPLIED WITH READ REQUESTS. PREFERABLY, FIRST AND SECOND COINCIDENCE CIRCUITS 51, 52 ARE COUPLED TO THE BUFFER ANTEMEMORY CIRCUIT AND RESPOND TO READ REQUESTS TO COMPARE ALL STORED MEMORY ADDRESS DATA WITH CONCERNING READING ADDRESS DATA CONTROL CIRCUITS 36, 37 PREFERREDLY PROCESS THE REQUEST FOR STORAGE IN BUFFER MEMORY BEFORE EACH REQUEST FOR READING. THE ANTEMEMORIES CIRCUIT MAY INCLUDE TWO PAIRS OF MEMORIES 41, 42; 63, 64, EACH PAIR STORING EACH OF THE STORAGE ADDRESS AND STORAGE DATA. AN ADDRESS CONVERTER 70 MAY BE ADDED TO CONVERT A LOGICAL ADDRESS REPRESENTED BY EACH ADDRESS DATA INTO A PHYSICAL ADDRESS.