Signature analysis system for testing digital circuits

摘要

A signature analyzer for testing digital circuits includes a memory which is initially programmed with a set of signatures characterizing the digital signals on the nodes of a correctly operating circuit. The nodes of a test circuit are then sequentially applied to a signature generator formed by a multi-stage shift register having the outputs of selected stages fed back to a gate to which the digital signal is applied. The signature generated by the shift register is compared to each of the signatures stored in memory until a signature match is found, thus indicating that the digital circuit, at least as far as the test node is concerned, is operating correctly. The signature generated by the shift register consists of twenty-four bits to provide a probability of error which is comparable to the probability of error in comparing a sixteen-bit signature with the signature from a specifically identified node. At the conclusion of a gate period. sixteen bits of the signature are displayed as four hexedecimal digits In order to minimize the probability of error, the analyzer also counts the number of transitions of the digital signal during the gate period and compares the count to transition counts stored in memory for the digital signals on the nodes of a correctly operating circuit. A comparison is then made of the transition count at the test node with each of the transition counts stored in memory. The analyzer thus ensures a transition count match as well as a signature match.