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PARALLEL TRIPLE SYSTEM CONSTITUTING METHOD OF COMPUTER SYSTEM

机译:计算机系统的并行三重系统构成方法

摘要

PURPOSE:To obtain an effective parallel triple system constituting method by applying this method to a small-scale processor such as a microcomputer, by providing a series-data transmission interface and fault decision circuit. CONSTITUTION:Input data to microcomputers 111 to 113 are collected and edited from controlled unit 130 via input-output interface 120. If a dissidence among input data is found through collation, they are made to coincide mutually following the fixed procedure. Next, respective computers 111 to 113 perform control logical operation and their results are compared with those of other systems. As a result, a fualt decision signal of ''0'' in case of the coincidence of output data or ''1'' in case of dissidence. On the basis of a status display signal in input data, it is discriminated whether or not there is a system recovering from its fault and when there is not, output data are sent to interface 120. When there is such a system, a decision on whether or not data collation results with other system agree is made; and in case of coincidence, they are outputted to interface 12 and in case of dissidence, an abnormality signal is outputted, thereby stopping the control.
机译:目的:通过将这种方法应用于诸如微型计算机之类的小型处理器,并提供串行数据传输接口和故障判定电路,从而获得有效的并行三重系统构成方法。组成:微计算机111至113的输入数据是通过输入输出接口120从受控单元130收集和编辑的。如果通过核对发现输入数据之间存在差异,则按照固定的过程使它们相互一致。接下来,各个计算机111至113执行控制逻辑操作,并将其结果与其他系统的结果进行比较。结果,如果输出数据一致,则最终判定信号为“ 0”,如果不一致,则最终判定信号为“ 1”。根据输入数据中的状态显示信号,判断是否存在从故障中恢复的系统,如果没有,则将输出数据发送到接口120。是否与其他系统的数据核对结果一致;在一致的情况下,将它们输出到接口12,在不一致的情况下,将异常信号输出,从而停止控制。

著录项

  • 公开/公告号JPS5931738B2

    专利类型

  • 公开/公告日1984-08-03

    原文格式PDF

  • 申请/专利权人 HITACHI LTD;

    申请/专利号JP19780090410

  • 发明设计人 UENO MASAHIRO;

    申请日1978-07-26

  • 分类号G06F11/18;G06F11/16;G06F15/00;G06F15/16;G06F15/177;

  • 国家 JP

  • 入库时间 2022-08-22 09:28:27

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