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METHOD OF AVOIDING UNDESIRABLE PARITY ERROR SIGNALS DURING THE PARITY CHECK OF A REGISTER ARRAY AND PARITY CHECK DEVICE FOR CARRYING OUT THE METHOD
METHOD OF AVOIDING UNDESIRABLE PARITY ERROR SIGNALS DURING THE PARITY CHECK OF A REGISTER ARRAY AND PARITY CHECK DEVICE FOR CARRYING OUT THE METHOD
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机译:在寄存器阵列的奇偶校验过程中避免不希望的奇偶校验错误信号的方法以及实现该方法的奇偶校验设备
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摘要
For a computer system having an array of external registers which may be used as a data source or data destination, wherein such system uses an odd parity checking system, and wherein certain of the register position in the external array can be vacant, an improved parity checking configuration includes a plurality of parity bit latches, one for each location in the external register array. The parity bit latches are set by an initial microprogram load to provide an odd parity bit for each location in the external array of registers which is empty or which may be faulty, disabled or malfunctioning. This assures that when the external array is searched by row, that all of the array locations will provide the appropriate parity check regardless of whether a byte of information exists therein or not.
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