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METHOD FOR AUTOMATIC TROUBLESHOOTING INSIDE VLSI CIRCUITS WITH AN ELECTRON PROBE AND DEVICE FOR CARRYING OUT SUCH A METHOD

机译:具有电子探针的超大规模集成电路内部自动故障排除的方法和实施该方法的装置

摘要

1. A method of detecting faults in VLSI-circuits (IC) using an electron probe (1) which triggers secondary electrons at test points in the VLSI-circuit (IC) - with a detector which, via a secondary electron signal, determines the actual level at the test points, - with a logic simulator (CAD-system VENUS and PRIMUS C) which serve to simulate the VLSI-circuit (IC) and to determine the theoretical level which is likely to occur at the test points with predetermined test patterns, - with a test computer (4) which controls a drive unit (2) for the VLSI-circuit (IC) and co-ordinates actual value and theoretical value, characterised in that, a) test points in the VLSI-circuit (IC) are assigned co-ordinates and the test points receive a designation and that the logic-links of the test points one in relation to another are determined, b) the VLSI-circuit (IC) is tested via the external terminals and fault paths are determined on the basis of the fault picture obtained from this test, c) the electron probe (1) is positioned at a first test point of a fault path, the appropriate test pattern is applied, and with the aid of the secondary electron signal the actual value at the test point is determined, d) the actual value at the test point is compared with the theoretical value obtained for the same test pattern from the simulation of the VLSI-circuit (IC) with the assistance of the logic simulator (CAD-system VENUS and PRIMUS C), e) the next test point in the fault path is tested in a corresponding manner and that f) the testing procedure is repeated at new test points in the test path until the fault location is localised.
机译:1.一种利用电子探针(1)检测VLSI电路(IC)中的故障的方法,该电子探针(1)在VLSI电路(IC)的测试点处触发二次电子,该电子探针具有检测器,该检测器通过二次电子信号确定逻辑模拟器(CAD系统VENUS和PRIMUS C)在测试点处的实际水平,该逻辑模拟器用于模拟VLSI电路(IC)并确定通过预定测试可能在测试点处发生的理论水平-用测试计算机(4)控制VLSI电路(IC)的驱动单元(2)并协调实际值和理论值,其特征在于:a)VLSI电路中的测试点( IC)被分配了坐标,并且测试点得到了一个名称,并且确定了测试点彼此之间的逻辑链接; b)通过外部端子和故障路径测试VLSI电路(IC)根据从该测试获得的故障图像确定,c)el ectron探头(1)放置在故障路径的第一个测试点上,应用适当的测试图案,并借助二次电子信号确定测试点处的实际值,d)将测试点与通过逻辑模拟器(CAD系统VENUS和PRIMUS C)借助VLSI电路(IC)的仿真从相同测试模式获得的理论值进行比较,e)以相应的方式对故障路径进行测试,并且f)在测试路径中的新测试点重复测试过程,直到确定故障位置。

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