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LIMITER WITH DYNAMIC HYSTERESIS.

机译:具有动态滞回作用的限制器。

摘要

limiter circuit (13) to increase the dynamic hysteresis insensitive to distortion at the output of the circuit in response to an input signal.the limiter circuit (13) includes a positive peak detector (15) and negative (17).weighted averages are obtained from both the positive and negative peaks, preferably by means of a voltage divider network (18).the first entry to a comparator circuit receives the input signal to the limiter circuit (13).different voltages from the voltage divider network (18) is applied to the second input of the comparator circuit (21) in such a way as to create a hysteresis effect with dynamic circuit comparateur (21). the different voltages are selected from the output voltage of the comparator circuit (21) by means of an analog switch (19).the circuit includes a voltage comparator (21) fixed to stabilize the valve hysteresis circuit (13) for input signals of low voltage.
机译:限幅器电路(13),以增加响应于输入信号对电路输出的失真不敏感的动态磁滞。限制器电路(13)包括正峰值检测器(15)和负峰值(17)。获得加权平均值最好通过分压器网络(18)从正峰值和负峰值中提取。比较器电路的第一个入口接收到限制器电路(13)的输入信号。来自分压器网络(18)的不同电压为施加到比较器电路(21)的第二输入端的方式是通过动态电路比较器(21)产生磁滞效应。通过一个模拟开关(19)从比较器电路(21)的输出电压中选择不同的电压。该电路包括一个电压比较器(21),该电压比较器被固定以稳定阀滞后电路(13)以获得低输入信号电压。

著录项

  • 公开/公告号EP0113766A4

    专利类型

  • 公开/公告日1984-11-20

    原文格式PDF

  • 申请/专利权人 MOTOROLA INC.;

    申请/专利号EP19830902499

  • 发明设计人 DOLIKIAN ARMAN VAHE;

    申请日1983-07-06

  • 分类号H03K5/08;H03K5/153;

  • 国家 EP

  • 入库时间 2022-08-22 08:03:47

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