首页> 外国专利> METHOD OF FABRICATING IMPURITY AREA SUPERIMPOSED WITH BORON AND DOPED BORON

METHOD OF FABRICATING IMPURITY AREA SUPERIMPOSED WITH BORON AND DOPED BORON

机译:掺硼和掺硼的杂质区的制备方法

摘要

A process for fabricating devices having overlapping heavily doped impurity regions of opposite conductivity wherein the formation of crystallographic faults emanating from the overlapping regions is eliminated. It has been discovered that crystallographic faults can be avoided by limiting the total N and P impurity concentrations in the overlapped regions. The process includes forming in the semiconductor substrate a first arsenic doped region having a maximum impurity concentration in the range of 5x1020 to 3x1021 atoms/cc, and forming in the silicon substrate a second adjacent boron doped region in partial overlapping relation to the first region having a maximum impurity concentration in the range of 5x1019 to 3x1020 atoms/cc.
机译:一种具有重叠的,具有相反电导率的重掺杂杂质区域的器件的制造方法,其中消除了从重叠区域发出的晶体学缺陷的形成。已经发现,可以通过限制重叠区域中的总N和P杂质浓度来避免晶体学缺陷。该工艺包括在半导体衬底中形成具有最大杂质浓度在5×1020至3×1021原子/ cc范围内的第一砷掺杂区域,以及在硅衬底中形成与第一区域部分重叠的第二相邻硼掺杂区域,该第二相邻硼掺杂区域具有部分重叠关系。最大杂质浓度在5x1019至3x1020原子/ cc的范围内。

著录项

  • 公开/公告号JPS6118856B2

    专利类型

  • 公开/公告日1986-05-14

    原文格式PDF

  • 申请/专利权人 INTAANASHONARU BIJINESU MASHIINZU CORP;

    申请/专利号JP19780152766

  • 发明设计人 INGURITSUDO IMESU MAGUDO;ARUMIN BOOGU;

    申请日1978-12-12

  • 分类号H01L29/73;H01L21/22;H01L21/223;H01L21/225;H01L21/331;H01L29/06;H01L29/36;

  • 国家 JP

  • 入库时间 2022-08-22 07:49:31

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号