PURPOSE:To perform space product sum arithmetic at a high speed by using two 1st shift registers for storage of the interim result of arithmetic and apply ing the outputs of both shift registers to the 2nd adder in the form of high-order 8 bits and low-order 8 bits respectively. CONSTITUTION:The F2 and F2, F1 and F2 and F0 and F2 are supplied with shifts to registers 38, 39 and 40 by shift clocks SCLK1-3 respectively. Then the sum of the 1st and 2nd arithmetic results of F1 and F1 is delivered from shift registers 24 and 25 respectively. The output of an adder 48 is equal to the space product sum arithmetic result of the F1 and F1 respectively. The above-mentioned arithmetic is repeated to set F255 and F2, F254 and F2 and F253 and F2 to registers 38-40 respectively. When the 3rd arithmetic is through with F254 and F1, the optional continuous 8 bits of the space product sum arithmetic results of F0,1-F255,1 are stored in a shift register 23. At the same time, the high-order 8 bits and low-order 8 bits are stored in the registers 24 and 25 respectively. This shortens the reading time and therefore increases the overall processing speed.
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