METHOD AND DEVICE FOR DECODING CYCLIC CODE

摘要

PURPOSE:To obtain a decoder where the number of shifts is reduced and increase of the quantity of hardware is reduced, by shifting contents of a prescribed feedback shift register to detect a burst error. CONSTITUTION:When a cyclic code generated in accordance with a generating polynominal expressed with a formula [Pi(x) is the irreducible polynominal of the mi order], a reception code F*(x) is inputted to the 0th - the l-th feedback shift registers (FSRC). These FSRCs are operated in accordance with plural dividers FSRP1-FSRP3, which divide this input by plural polynominals such as (xc+1), etc., and an AND output 171 between the output of a lower bit coincidence detecting circuit consisting of coincidence decision circuits 323-325, etc. and a coincidence detector 326 which decides whether upper bits are all ''0'' or not. Contents of one or more FSRCs are shifted a prescribed number of times, and FSRCs are shifted simultaneously until said coincidence detectors detect coincidence of lower bits and all ''0'' of upper bits, thus detecting the burst error.