BIT SERIAL CONVOLUTIONAL DECODER FOR VLSI IMPLEMENTATION

摘要

27284-3?ABSTRACTA decoder for forward-error-correcting (FEC) convolutionalcodes. The decoder uses the Viterbi algorithm for decoding therate ?,constraint length 7 code with generator polynomials x6+x5+x3+x2+1, and x6+x3+x2+x+1. The architecture of the instant decoderis appropriate for implementation on a single monolithic VLSIintegrated circuit chip and includes a branch metric calculatorcircuit which produces output signals representative of input sym-bol signals. These output signals are supplied to a metric updatecircuit which evaluates the signals from the calculator circuitand provides decisions to a path update circuit which convergesthe signals thereto and the output signals of which are evaluatedby a majority vote circuit which produces data output signals repre-sentative of data input signals.