ANTEMEMORY UNIT WITH DEVICE FOR SIMULTANEOUSLY READING INSTRUCTIONS

摘要

A data processing system comprises a data processing unit coupled to a cache unit r which couples to a main store. The cache unit (Fig. 4 not shown) includes a cache store (750-300) organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes control apparatus, (750-5) an instruction buffer (750-7) for storing instructions received from main store and a transit block buffer (750-102) comprising a plurality of locations for storing read commands. The control apparatus includes a plurality of groups of bit storage elements corresponding to the number of transit buffer locations. Each group includes at least a pair of instruction fetch indicator elements which are operatively connected to control the writing of first and second blocks of instructions into the instruction buffer. Each time a read command specifying the fetching of instructions of either a first or second block is received from the processing unit, the flag storage element associated with the transit block buffer location into which the read command is loaded is set to a binary ONE state while the corresponding ones of the flag storage elements associated with the other locations storing outstanding read commands specifying instruction fetches are reset to binary ZEROS. This permits only those instructions received from main store in response to that read command to be loaded into a specified section of the instruction buffer for enabling overlaps in processing several commands specifying instruction fetch operations. The instruction buffer has first and second sections (750-715, 750-717) for storing instructions received from main store. Each instruction buffer section includes a plurality of word storage locations, each location having a number of bit positions. A predetermined bit position of each location is used to indicate when an instruction word has been written into the location. Control apparatus coupled to each of the buffer sections is operative to reset all of the word locations to binary ZEROS when a command requesting an instruction block from main store is ready to be transferred thereto. It is set to a binary ONE state when an instruction word is loaded into the location. Instruction buffer ready circuits included within the control apparatus are conditioned by the states of the predetermined bit positions of the locations to generate output signals to the processing unit enabling the transfer of requested instruction words to the processing unit as soon as they are received from main store.