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synthesizer of frequencies a fractional division, a small phase jitter and use of this synthesizer

机译:频率合成器,分数除法,小相位抖动以及该合成器的使用

摘要

The invention relates to a synthesizer a fractional division, a small phase jitter. / p & & p & such a synthesizer comprises a controlled oscillator 11 supplying a signal of frequency f; a phase comparator receiving a reference signal supplied by an oscillator and a divider 6 and receiving a signal of frequency fsrv supplied by a variable order divider to 8; a phase accumulator 7 adding a constant increment k, at the frequency of the reference signal; a device 10 for converting the analog, 1984, -, and for correcting the value supplied by the phase accumulator 7, an adder 15 receiving a current supplied by the phase comparator 9 and a current supplied by the device 10 for the conversion, 1984, - analog correction; means 14, 13, 12, 29 for to integrate and filter a current supplied by the adder 15 and to control the slaved oscillator 11. The synthesizer according to the invention comprises a device 10 for the conversion, 1984, - analog correction, comprising a plurality of delay devices, each receiving a fraction of the binary word c supplied by the output of the phase accumulator 7, and supplying a logic signal of time proportional to the value of this fraction of the binary word c and proportional to the period 1fs; a plurality of current sources, each providing a national corresponding respectively to the maximum value of one of the fractions of the binary word c; a plurality analog switches, respectively connecting the sources has an adder and since ordered respectively by the devices of the time delay. / p & & p & application, in particular, to 29.
机译:本发明涉及一种分数除法,小相位抖动的合成器。 & &这种合成器包括提供频率为f的信号的受控振荡器11。相位比较器接收由振荡器和除法器6提供的参考信号,并接收由可变阶除法器提供给8的频率fsrv的信号;相位累加器7以参考信号的频率加上恒定的增量k。 -用于转换模拟量1984的装置10,以及用于校正由相位累加器7提供的值的装置,加法器15接收由相位比较器9提供的电流和用于转换的装置10提供的电流1984, -模拟校正;装置14、13、12、29用于积分和滤波加法器15提供的电流并控制从属振荡器11。根据本发明的合成器包括用于转换的装置10,1984,-模拟校正,包括:多个延迟装置,每个延迟装置接收由相位累加器7的输出提供的二进制字c的分数,并提供与该二进制字c的该分数的值成正比且与周期1fs成比例的时间逻辑信号;多个电流源,每个电流源提供分别对应于二进制字c的小数之一的最大值的国家;分别连接源的多个模拟开关具有加法器,并且由于分别由时间延迟装置排序。 & &尤其是29。

著录项

  • 公开/公告号FR2557401B1

    专利类型

  • 公开/公告日1986-01-24

    原文格式PDF

  • 申请/专利权人 THOMSON CSF;

    申请/专利号FR19830020844

  • 申请日1983-12-27

  • 分类号H03J7/06;

  • 国家 FR

  • 入库时间 2022-08-22 07:31:25

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