Phase-lock loop circuit providing very fast acquisition time

摘要

The present invention relates to a very fast acquisition phase- lock loop arrangement comprising means for generating an error signal between an input signal to the loop and an output signal of a voltage controlled oscillator (VCO). The generated error signal, over its possible range of phase differences, is transformed by a transforming means into an output signal comprising a predetermined nonlinear response. The output signal from the transforming means is integrated in an integrating means to generate a control signal for appropriately changing the output signal of the VCO. Noise performance can be significantly improved by cascading two or more of the present phase-lock loop arrangements.