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Fast acquisition phase-lock loop

机译:快速采集锁相环

摘要

A PLL frequency detector or comparator is provided having an up-down counter, responsive to beat signals produced by the input periodic waveforms of the VCO reference signals and the input data signals, to produce top and bottom output signals which enable multivibrators connected to each of the input signal lines to transmit overflow and underflow output pulses, whose sum is proportional to the difference in frequency of the input signals up to a predetermined maximum level, as control signals for the PLL loop filter. The up-down counter may include three or more states with buffer states which prevent generation of overflow or underflow output signals when the PLL is within a predetermined region of phase-lock and the sign of the beat signal oscillates. The up-down counter may also be employed simultaneously as a phase detector or comparator, wherein the top and bottom output signals are combined so as to produce control signals for the PLL loop filter when the overflow and underflow output signals are not generated.
机译:提供了一个PLL频率检测器或比较器,该计数器具有一个上下计数器,以响应由VCO参考信号的输入周期波形和输入数据信号产生的差拍信号,产生顶部和底部输出信号,从而使多谐振荡器连接到每个输入信号线传输上溢和下溢输出脉冲,作为PLL环路滤波器的控制信号,其总和与输入信号的频率差直至预定的最大电平成正比。上下计数器可以包括具有缓冲器状态的三个或更多个状态,当PLL处于锁相的预定区域内并且拍频信号的符号振荡时,该状态可以防止产生上溢或下溢输出信号。上下计数器也可以同时用作相位检测器或比较器,其中在未产生上溢和下溢输出信号时,将顶部和底部输出信号进行组合,以产生用于PLL环路滤波器的控制信号。

著录项

  • 公开/公告号US4587496A

    专利类型

  • 公开/公告日1986-05-06

    原文格式PDF

  • 申请/专利权人 GENERAL SIGNAL CORPORATION;

    申请/专利号US19840649677

  • 发明设计人 DAN H. WOLAVER;

    申请日1984-09-12

  • 分类号H03L7/10;H03D13/00;

  • 国家 US

  • 入库时间 2022-08-22 07:29:15

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