PLL TYPE OFFSET FREQUENCY SYNTHESIS CIRCUIT

摘要

PURPOSE:To obtain a PLL type offset frequency synthesizer not requiring a filter by providing a maximum value circuit selecting a larger output of the 1st and 2nd phase comparator circuits and a voltage controlled oscillator using an output of the maximum circuit as a control voltage. CONSTITUTION:An offset frequency signal in a frequency signal f0 and a signal having a frequency fm=fv-Fc being the result of mix-down between an output of a voltage controlled oscillator (VCO) 4 in a frequency fv and a RF sinusoidal wave CW in a frequency fc are inputted to a phase comparator 1. When a frequency of the VCO 3 is changed, the relation of fmf0 exists with fc-f0fc+ f0 and the relation of fmf0 exists with fv=fc-f0 or fc+f0=fv, then an output frequency of the VCO 4 and an output voltage 10 of the comparator 1 are obtained. Similarly, the output frequency of the VCO 4 and an output voltage 20 are obtained.The outputs 10 and 20 of phase compartors 1, 2 are inputted to a maximum value circuit 3 to obtain the VCO output frequency and an output 30 of the maximum circuit 3 in a prescribed relation and only when the VCO output frequency is fc+f0, the PLL is locked.