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CONTROL SYSTEM FOR INSTRUCTION TRAIN OF INTERMEDIATE LANGUAGE

机译:中级语言教学控制系统

摘要

PURPOSE:To improve register allotment efficiency in a compiling mode by interposing a virtual basic block and regarding a next basic block substantially as the virtual basic block. CONSTITUTION:The basic block dictionaries are prepared for basic blocks A, B... respectively and the information on the connecting relation is held as shown by a basic block train 1. As shown in a diagram, the basic block corresponding to the loop exit is defined as a block D with the next basic block E defined as branch destinations from blocks D and A respectively according to the contents of the corresponding basic block dictionary. This processing is carried out by a check processing part 2. In an example shown in the diagram, a virtual basic block insertion processing part 3 is actuated for the interpolation of a virtual basic block X. Thus the destination of the block D is equal to the block X and the next basic block is also equal to the block X. This prevents the deterioration of the processing efficiency.
机译:目的:通过插入虚拟基本块并将下一个基本块视为虚拟基本块来提高编译模式下的寄存器分配效率。组成:基本块字典分别为基本块A,B ...准备,并且保持连接关系的信息,如基本块序列1所示。如图所示,对应于循环出口的基本块根据相应的基本块字典的内容,将“ D”定义为块D,将下一个基本块E定义为分别从块D和A的分支目的地。该处理由检查处理部分2执行。在该图中所示的示例中,虚拟基本块插入处理部分3被致动以对虚拟基本块X进行插值。因此,块D的目的地等于块X和下一个基本块也等于块X。这防止了处理效率的降低。

著录项

  • 公开/公告号JPS61256447A

    专利类型

  • 公开/公告日1986-11-14

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19850098485

  • 发明设计人 NAKANISHI MAKOTO;

    申请日1985-05-09

  • 分类号G06F9/44;G06F9/45;

  • 国家 JP

  • 入库时间 2022-08-22 07:25:45

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