PURPOSE:To perform the leap field signal detection processing at a lower speed to reduce the cost of a circuit by deciding whether the total number of data '1' exceeds a prescribed value or not with respect to individual bits of pairs of parallel data bits. CONSTITUTION:Four-phase demodulated time base-compressed symbols (p) and (q) are given to control inputs of counters CT 12a and 12b as a new pair of parallel bits by a differential demodulating circuit 11, and CTs 12a and 12b count the number of times of rise of clocks if both control inputs are in the high level. The initial value of a setter 13 is loaded just before the start of counting, and an overflow signal is outputted as a leap field signal decision result to set an FF 14 when the sum of the initial value and counted values exceeds the prescribed value. By the output of the FF 14, the signal discrimination result is transmitted as a timing control signal just after the period when a leap field signal appears.
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