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MULTIVALUED LOGICAL MULTIFUNCTION CIRCUIT

机译:多值逻辑多功能电路

摘要

PURPOSE:To execute simultaneous operation of plural different multivalued logical operations possible by providing address lines of a memory array and an addressed switch for plural multivalued logical functions, and connecting these address lines to output lines corresponding to plural multivalued logical functions in a sum array. CONSTITUTION:At the time of combination of input x and y is given, signals that indicate four different functions f1-f4 that indicate the result obtained by calculating the input x, y conforming to a truth value table are obtained. In such a multifunction circuit, it is necessary to program a sum array 24 in addition to a memory array 21 and an AND array 22. In a circuit shown in the figure, it is possible to omit the number of column lines furthermore. For instance, when the line of the second column and the line of the fortieth column connected to an output terminal 38 are connected by a node shown by B, entirely the same output signals are obtained in output terminals 35 and 38 even if the line of the fortieth column is removed.
机译:目的:通过提供存储器阵列的地址线和用于多个多值逻辑功能的寻址开关,并将这些地址线连接到总和阵列中与多个多值逻辑功能相对应的输出线,来执行多个不同的多值逻辑运算的同时操作。组成:在给出输入x和y的组合时,获得了表示四个不同函数f1-f4的信号,这些函数表示通过计算符合真值表的输入x,y而获得的结果。在这种多功能电路中,除了存储器阵列21和与阵列22之外,还需要对和阵列24进行编程。在该图中所示的电路中,可以进一步省略列线的数量。例如,当连接到输出端子38的第二列的线和第四十列的线通过由B所示的节点连接时,即使输出线35的线与输出端子35和38也获得完全相同的输出信号。第四十列被删除。

著录项

  • 公开/公告号JPS62203232A

    专利类型

  • 公开/公告日1987-09-07

    原文格式PDF

  • 申请/专利权人 OMRON TATEISI ELECTRONICS CO;

    申请/专利号JP19860045466

  • 发明设计人 YAMAKAWA RETSU;

    申请日1986-03-04

  • 分类号G06F7/60;H03K19/20;

  • 国家 JP

  • 入库时间 2022-08-22 07:24:43

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