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TEST SYSTEM FOR VLSI DIGITAL CIRCUIT AND METHOD OF TESTING

机译:VLSI数字电路的测试系统和测试方法

摘要

ABSTRACT OF THE DISCLOSUREA method of testing the conductive state of atransistor in a semiconductor integrated circuit compris-ing the steps of applying electrical power through loadmeans to the integrated circuit, applying a clock signalto the integrated circuit, stopping the clock signal at apredetermined time period, irradiating the transistor witha focused radiation beam, and measuring change in currentapplied to the integrated circuit by correlated doublesampling whereby voltages at either end of the load meansare capacitively coupled to differential amplificationmeans measuring change in voltage at either end of theload means. Also disclosed is a test apparatus forcarrying out the method.
机译:披露摘要测试导体导电状态的方法半导体集成电路中的晶体管包括通过负载施加电力的步骤指向集成电路施加时钟信号到集成电路,将时钟信号停止在在预定的时间段内,向晶体管照射聚焦辐射束,并测量电流变化通过相关双应用于集成电路采样,负载两端的电压表示电容耦合至差分放大表示测量两端的电压变化加载方式。还公开了一种用于执行该方法。

著录项

  • 公开/公告号CA1222329A

    专利类型

  • 公开/公告日1987-05-26

    原文格式PDF

  • 申请/专利权人 DATAPROBE CORPORATION;

    申请/专利号CA19840467825

  • 发明设计人 HENLEY FRANCOIS J.;

    申请日1984-11-14

  • 分类号G01R31/28;

  • 国家 CA

  • 入库时间 2022-08-22 07:16:49

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