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VERY LARGE SCALE INTEGRATED CIRCUIT SUBDIVIDED INTO ISOCHRONOUS REGIONS, METHOD FOR THE MACHINE-AIDED DESIGN OF SUCH A CIRCUIT, AND METHOD FOR THE MACHINE- AIDED TESTING OF SUCH A CIRCUIT
VERY LARGE SCALE INTEGRATED CIRCUIT SUBDIVIDED INTO ISOCHRONOUS REGIONS, METHOD FOR THE MACHINE-AIDED DESIGN OF SUCH A CIRCUIT, AND METHOD FOR THE MACHINE- AIDED TESTING OF SUCH A CIRCUIT
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机译:细分为等速区域的超大规模集成电路,这种电路的机器辅助设计方法以及这种电路的机器辅助测试方法
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33ABSTRACT:Very large scale integrated circuit subdivided into isochronous regions,method for the machine-aided design of such a circuit, and method forthe machine-aided testing of such a circuit.A very large scale integrated circuit comprises a number offunction blocks which are synchronized by relevant clock signals. Eachfunction block forms an isochronous region so that the delay times ofthe signals within the relevant function block can be negligibly smallwith respect to the gate delay tubes. Each function block is pairedwith at least one other function block in that the pair is connectedby an information connection and by at least two synchronizationhandshake lines for transporting synchronization signals despatchedby each function block of the pair to the other function block of thepair so that an asynchronous information transport is obtained. One ormore of the function blocks comprises an information connection to theenvironment. As a result of this set-up, the circuit can also betested and designed per function block.
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