DIGITAL DATA PROCESSOR WITH SYSTOLIC ARRAY OF PIPELINED BIT-LEVEL PROCESSING CELLS

摘要

ABSTRACTA digital data processor is provided to multiply data elements bycoefficients. It includes a systolic array of cells consisting ofnearest neighbour connected gated full adders. The cells multiplydata bits received from laterally adjacent cells and subsequentlypass them on. The product is added to a cumulative sum bit from acell above and to a carry bit recirculated from an earlier compu-tation. The output is passed to a cell below, and a new carry bit isrecirculated for addition in a subsequent computation. Data andcoefficients are input in counterflow to opposite sides of the array.An adder tree accumulates non-simultaneously computed contributionsto individual output terms. The tree incorporates a delay andswitches arranged to implement or bypass the delay according toearlier or later computation of a contribution. By virtue of thisaccumulation, the processor provides reduced cell redundancy comparedto the prior art.