Circuit for speeding up transfers of charges in programmable logic array structures

摘要

@ Circuit for speeding up transfers of charges in a Programmed Logic Array structure, formed by FET devices (3) in serially chained charge transfer circuits, comprising a level shifting circuit (21) integrated into bit partitioning stages of the structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings at the inputs of the AND array chains (24) as well as decreasing operational delays of the latter stage, discrete capacitance, (29), added at the output end of the OR array stage (10) for sustaining and reinforcing charge conditions accumulated in that stage prior to readout of that stage, and a source of time related clocking functions (Cp1-Cv3) coupled to stages of the modified structures, with the timing relationship selected so as to reduce operational delays of the entire structure while improving its integrity of operation.