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Sampling waveform digitizer for dynamic testing of high speed data conversion components

机译:采样波形数字化仪,用于高速数据转换组件的动态测试

摘要

A sampling digitizer system which may be expanded for the dynamic testing of high speed data conversion components is provided. The system includes latching comparators which are supplied with the waveform under test and the comparator digital output is integrated by an operational amplifier integrator and fed back to the reference input of the latching comparator to form a comparator-integrator loop. A circuit provides strobe pulses which repeatedly sample the latch enable input of the comparators at a selected time/point until the integrator feedback forces the comparator reference input to be equal to the sample value of the input signal. At this point, an equilibrium state is reached where the integrator output oscillates about the sampled value, and when the loop settles, an analog-to-digital converter reads the final value under computer command. The sample point is computer controlled through a programmable delay line. A modified T-filter system operatively coupled between the output of the latching comparator and the input of the operational amplifier allows control of the integrator slope and filters out signal spikes to allow the required accuracy for high speed measurements while a similar modified T-filter is provided in the feedback loop for preventing disturbances at the integrator output which could be caused by the sampling of the latching comparators and for simultaneously preventing ringing and for rounding off signal spikes in the feedback loop. Various adaptions of the broad sampling digitizer system are provided for measuring the settling time of a 12-bit digital- to-analog converter whose common mode output reading is one-half LSB accuracy in under 40 nanoseconds and a dynamic tester for very fast- acting sample and hold amplifier circuits which measure, by independently controlling the polarity of the square wave or test stimulus signal and the polarity of the hold select command, such circuit parameters as acquisition time, sample-to-hold settling time, sample-to-hold offset, glitch amplitude, amplitude delay, hold mode feedthrough rejection, risetime, slew rate, and the like.
机译:提供了可以扩展用于高速数据转换组件的动态测试的采样数字转换器系统。该系统包括被提供测试波形的锁存比较器,比较器数字输出由运算放大器积分器积分,并反馈到锁存比较器的参考输入,以形成比较器积分器环路。电路提供选通脉冲,该选通脉冲在选定的时间/点重复采样比较器的锁存使能输入,直到积分器反馈迫使比较器参考输入等于输入信号的采样值为止。此时,达到平衡状态,积分器输出在采样值附近振荡,当环路建立时,模数转换器在计算机命令下读取最终值。采样点由计算机通过可编程延迟线控制。改进的T滤波器系统可操作地耦合在锁存比较器的输出和运算放大器的输入之间,从而可以控制积分器的斜率并滤除信号尖峰,以实现高速测量所需的精度,而类似的改进T滤波器则是在反馈回路中提供了一个功能,用于防止积分器输出处的干扰(可能由锁存比较器的采样引起),并同时防止振铃并消除反馈回路中的信号尖峰。提供了广泛的采样数字化仪系统的各种适应方案,用于测量12位数模转换器的建立时间,该转换器的共模输出读数在40纳秒内为LSB精度的一半,而动态测试仪的响应速度非常快采样保持放大器电路,通过独立控制方波或测试激励信号的极性以及保持选择命令的极性来测量电路参数,例如采集时间,采样保持时间,采样保持偏移,毛刺幅度,幅度延迟,保持模式馈通抑制,上升时间,压摆率等。

著录项

  • 公开/公告号US4641246A

    专利类型

  • 公开/公告日1987-02-03

    原文格式PDF

  • 申请/专利权人 BURR-BROWN CORPORATION;

    申请/专利号US19830543853

  • 发明设计人 MYRON J. KOEN;JOEL M. HALBERT;

    申请日1983-10-20

  • 分类号G01R23/16;G06F15/31;

  • 国家 US

  • 入库时间 2022-08-22 07:09:43

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