Circuit design technique to prevent current hogging when minimizing interconnect stripes by paralleling STL or ISL gate inputs

摘要

An STL or ISL logic circuit comprising a plurality of single- input, multiple-output logic gates is provided. Each of these gates has a current source and a transistor including a base, emitter and multiple Schottky diode-to-collector contacts. The bases of the logic gate transistors are tied together to minimize metal interconnect stripes when a fanout greater than that of one gate is needed. Current hogging is reduced by an ohmic collector contact with connects the collector of each transistor together.